A sense amplifier is electronic circuitry which is typically included in a memory component in an electronic device, and which accomplishes the reading of the state of memory cells in the memory. This reading process depends on how much current a memory cell sinks under well-defined biasing conditions. The task of a sense amplifier is to transform this current information into binary information that is suitable to be used as internal digital memory data. In the simplest case, the binary information consists of two logical levels (“1” or “0”), which respectively correspond to the memory cell states in which the cell sinks or does not sink a current under well-defined biasing conditions.
One way to read the cell state is to compare the cell current (Icell) with a reference current (Iref), usually provided by another cell, and track the process characteristics of the memory cell. The reference cell usually sinks a current having a value placed between the cell current in the logical state “1” and the cell current in the logical state “0.” For example, if the memory cell in the state “0” sinks no current, the reference cell could sink one half of the cell current in the logical state “1.” The sense amplifier reads the difference between the cell current and the reference current, transforming it into binary information suitable to be used by the other memory chip circuits. For example, the current difference can be positive or negative if the cell state is “1” or “0,” respectively, so that the sense amplifier generates a binary signal “1” or “0,” respectively.
FIG. 1 illustrates a conventional scheme for a sense amplifier system 10. The elements 500, 600, 530, and 630 are not parts of the sense amplifier itself, but these elements schematically depict the cell memory array. Memory cell 500 is a cell of which it is wanted to know the state, and reference cell 600 is provided as the reference. These cells typically are linked to the sense amplifier circuitry by bit-lines 530 and 630, respectively. In order to allow the cells 500 and 600 to conduct their currents, the voltages of the gates 510 and 610 and the drains 520 and 620 must be brought to an opportune voltage value. In particular, the drain voltages are set by the sense amplifier circuitry, using the feedback configuration build-up with the inverters 310 and 410. In other embodiments, other methods can be used to ensure the correct polarization of the drain voltages. The inverters ensure that an opportune voltage value (for example, about 1V) is set on the nodes 540 and 640 as well on the nodes 520 and 620 placed at the end of the bit lines 530 and 630, respectively. A pass gate 700, controlled by enable signal 710, keeps the nodes 800 and 900 at the same voltage value only for an initial transient period called the “equalizing phase.” During this phase, the transistor 200 sets the node 900 voltage and, via the pass gate 700 with transistor 100, also sets the node 800 voltage. In fact, since the transistor 200 is in a diode configuration, a well-defined relation exists between its gate-to-source voltage and the drain current:
                              I          ds                =                                            μ              ⁢                                                          ⁢                              C                ox                                      2                    ⁢                      W            L                    ⁢                                    (                                                V                  gs                                -                                  V                  th                                            )                        2                                              (        1        )            
where Ids is the drain-to-source current, μ is the carrier mobility, Cox is the gate oxide capacitance per unit area, W and L are respectively the width and the length of the transistor, Vgs is the gate to source voltage, and Vth is the threshold voltage. For a given Ids, the node 900 voltage value is determined since its value coincides with Vgs of the transistor 200 as appearing in Equation (1).
A first simplified analysis of the circuit is now presented for the “steady state” condition, in which all the currents and voltages are settled. Once this state is reached, the transistors 300 and 400 sink the cell current and the reference current, respectively. The transistors 100 and 200 constitute the well-known mirror configuration, that is, all the current passing through the transistor 200 is transferred to the transistor 100. Once the pass gate 700 is turned off, the transistor 200 supplies the reference cell current through the transistor 400. Transistor 200, in turn, transfers it to the other side of the circuit by the transistor 100. The node 800 receives the reference current from the transistor 100 and the cell current from the transistor 300. Therefore, starting from a voltage fixed by the transistor 200 during the equalization phase, the node 800 evolves as driven by the current difference (Iref−Icell), following this simple law:
                              Δ          ⁢                                          ⁢                      V            800                          =                                                            (                                                      I                    ref                                    -                                      I                    cell                                                  )                            ·              Δ                        ⁢                                                  ⁢            T                                C            800                                              (        2        )            
where ΔV800 is the voltage difference of which the parasitic capacitance of the node 800 (referred to as C800) is charged, or discharged, by the current difference (Iref−Icell) after the time ΔT. C800 is the sum of the parasitic capacitance of the transistors coupled to the node 800 plus the parasitic capacitance of the interconnecting metals of component connections. It is worth noticing that, in Equation (2), Iref and Icell are assumed constant in time because the steady state condition is presumed to have been reached for this simplified analysis. The voltage level of the node 900 accurately represents the reference current because the node's value directly depends on the Iref value according to Equation (1), while the voltage level of the node 800 accurately represents the cell current because node 800 is charged or discharged, with respect to its starting value, depending on the cell current value. If, for simplicity, C800 is called Cout, the equation for Vout becomes:
                              V          out                =                                                                              (                                                            I                      ref                                        -                                          I                      cell                                                        )                                ·                Δ                            ⁢                                                          ⁢              T                                      C              out                                .                                    (        3        )            
Vout has a positive sign if the circuit is sensing a “0,” negative if is sensing a “1,” and its magnitude grows with time. This voltage difference is suitable to be used as input for the comparator 1000, which amplifies it in order to have a full swing signal (i.e. GND or Vdd). The amplified form of the signal provides the binary information needed and suitable to be used for the internal binary data exchange; conventionally, the full swing signal at Vdd or GND respectively corresponds to the logical level “1” or “0.”
The above analysis is for the simple case in which only the steady state currents pass through the transistors. Unfortunately, the steady state condition may take a long time to be reached, especially if high capacitive bit-lines link the cells to the sense amplifier circuitry and the cell current is very low. During a transient period, called “precharging phase” (which begins when the currents from the main path transistors start to charge bitlines and ends once the precharging currents becomes negligible with respect to the cells currents), a current passes through the bit-lines to bring up the drains of the cells to the desired voltage level (about 1 V). This phase must take the shorter possible time; thus, the width of transistors 100, 200, 300, and 400 must be large enough to supply all the required precharging current from Vdd. At the beginning of the phase this current reaches a peak, proportional to the bit-line capacitance value, and then the current drops to zero and only the steady state current passes through the transistors 300 and 400. Once the pass gate 700 is turned off, the node 800 changes, as depicted by Equation (2), with a speed inversely proportional to the value of C800. Since the transistors 100 and 300 may be quite large, C800 can also be quite large and the node 800 may not change fast enough to allow the desired reading performance of the system. Moreover, the current difference (Iref−Icell) can be very small, driving the node 800 with a very low strength. In conclusion, this simple sense amplifier scheme can be unsuitable to read the data in a fast way, especially in the case in which long bit-lines link the cells to the sense amplifier circuitry and the current difference (Iref−Icell) is very small.
Another approach for a sense amplifier system 20 is shown in FIG. 2. A folded stage is added to the system of FIG. 1 to improve the speed with which the output node evolves after the equalizing phase. The transistors 100 and 110, and transistors 200 and 210, are in a mirror configuration, in which the current passing through the transistors 100 and 200 is transferred to the folded stage by the transistors 110 and 210, respectively. During the equalizing phase, the transistor 220 sets the node 910 voltage value according to Equation (1) and, via the pass gate 700, together with transistor 120, also sets the node 810 voltage. Once the steady state is reached, the transistors 210 and 110 respectively supply the reference and the cell currents to the folded stage. When the pass gate 700 is turned off, the node 810 receives the cell current via the transistor 110 and, since the transistors 220 and 120 are in a mirror configuration, receives the reference current via the transistor 120. The node 810 thus evolves driven by the current difference (Icell−Iref) as depicted by the following equation:
                              Δ          ⁢                                          ⁢                      V            810                          =                                                            (                                                      I                    cell                                    -                                      I                    ref                                                  )                            ·              Δ                        ⁢                                                  ⁢            T                                C            810                                              (        4        )            
The evolution speed of the node 810 depends on the value of its capacitance C810. Equation (4) is similar to Equation (2) that depicts the behavior of the scheme in FIG. 1; therefore, to obtain an improvement with respect to the previous scheme, C810 must be quite smaller than C800 appearing in Equation (2). Disregarding the interconnecting metals, the main component of C810 is due to the parasitic capacitance of the transistors 110 and 120 coupled with the node 810. The smaller are these transistors, the less capacitive is the node. It is not convenient to reduce the size of the transistor 110 too much because it transfers the cell current in the folded stage: if, for example, 110 were n times smaller than 100, the current transferred in the folded stage would be n times smaller, since 110 and 110 are two mirror connected transistors. This is not advisable since the Icell value could be very small. Instead, it is possible to provide a smaller transistor 120 because it does not have to supply the precharging current as supplied by the transistors in the main circuit path. The node 810 then can be much lower in capacitance than node 800 and, when pass gate 700 is turned off, node 810 can evolve faster than the node 800 of the circuit in FIG. 1. If, for simplicity, C810 is called Cf,out, the equation for Vout becomes:
                              V          out                =                                                            (                                                      I                    cell                                    -                                      I                    ref                                                  )                            ·              Δ                        ⁢                                                  ⁢            T                                C                          f              ,              out                                                          (        5        )            
where Cf,out is much less than Cout appearing in Equation (3). Vout has a positive sign if the circuit senses a “1”, negative if it senses a “0.”
However, the scheme of FIG. 2 has other issues involving the transient behavior of the folded stage itself. During the bit-line precharging phase, the transistors 100 and 200 supply, to the transistors 110 and 210 respectively, the cell and the reference currents (Icell and Iref), plus the corresponding bit-line precharging current or, in a more general case, any other transient currents. Even once the pass gate 700 is turned off, the global current coming from the cell and the reference sides of the main circuit can vary in time due to all the above mentioned transient currents. As a consequence, the transistor 220 must continuously adapt its biasing conditions to lead the supplied current, transferring the supplied current to the mirror connected transistor 120. Its gate-to-source voltage must adapt the current injected from the transistor 210 according to Equation (1). Therefore, the parasitic capacitance of the node 910, called C910, must be charged or discharged in order to reach the correct biasing condition. This generates a spurious current component, called IC910, relative to the charge transfer on the node 910. Since the transistors 220 and 120 are in a mirror configuration, the current IC910 is supplied to the node 810 which evolves as it is driven also by this current component. Calling the global currents supplied respectively from the cell and references sides of the main circuit Icell,side (Icell plus any transient currents) and Iref,side (Iref plus any transient currents), the equation for the node 810 becomes:
                              Δ          ⁢                                          ⁢                      V            810                          =                              1                          C              810                                ⁢                      ∫                                          [                                                                            I                                              cell                        ,                        side                                                              ⁡                                          (                      t                      )                                                        -                                                            I                                              ref                        ,                        side                                                              ⁡                                          (                      t                      )                                                        -                                                            I                                              C                        ⁢                                                                                                  ⁢                        910                                                              ⁡                                          (                      t                      )                                                                      ]                            ⁢                              ⅆ                t                                                                        (        6        )            
It is worth noticing that the integral form in Equation (6) is needed because all the terms in the equation are varying in time (neglecting, for sake of simplicity, the fact that the capacitance C810 also varies in time due to the different biasing conditions of the transistors 110 and 120). It should also be pointed out that the exact behavior of any transient currents coming from the main circuit (including transistors 100 or 200), and their repercussion on the reading performance, is out of the scope of this analysis. Starting from the above equation, is possible to focus the analysis on the folded circuit behavior under the influence of the capacitive current component IC910. As shown by Equation (6), the latter term is the only current component, depending on the folded stage itself, that can cause an incorrect data read. This current is generated by some transient behavior and then it diminishes to zero at the steady state. This spurious current component can destroy the correct data information acquired from the cell. In the analysis below, the steady state behavior of the circuit (depicted by Equation (4) and set forth as the target behavior) is compared with the behavior depicted by Equation (6).
Depending on the charging or discharging of the node 910, two cases can be analyzed. However, for sake of simplicity and without loss of generality, only the case in which the node 910 is discharging is here analyzed. The extra current required to perform the discharge is supplied by the transistor 220 and then transferred to the node 810 by the mirror connected transistor 120. As a result, the term Ic910 in Equation (6) is positive, having the effect of discharging the node 810. Reading a “0” (Icell<Iref), the circuit behavior at the steady state would be to discharge the node 810, as depicted by Equation 4. In Equation (6), it is shown that the current Ic910 helps to discharge this node. Therefore, this current does not cause any dangerous effect reading a “0,” or rather the read operation receives advantage from this spurious current. On the contrary, reading a “1” (Icell>Iref), the steady state behavior (still described by Equation (4)) is to charge the node 810, driven by the positive current difference (Icell−Iref). Instead of this, as shown by Equation (6), the node 810 could be discharged by the current IC910; this occurs if this current's value is not negligible with respect to the current difference (Icell−Iref). As a consequence, the term IC910 can change the correct behavior of the circuit: while IC910 is greater than the difference (Icell−Iref), the node 810 is initially discharged and, only once the node 910 is about to reach its steady state value (that is IC910<(Icell−Iref)), can the node 810 charge correctly start to rise. Therefore, when reading a “1,” the Vout signal may be incorrect at the beginning of the transient behavior and indicate a “0” state, and become correct only once the spurious current is almost faded out.
Thus, the issue of spurious current becomes important especially when a sense amplifier is designed to read a very low current difference between the cell and the reference currents. In fact, in this case, the capacitive current IC910 may not be negligible with respect to this difference, causing incorrect data acquisition until it reaches almost a zero value. In particular, the issue involves the case in which the cell current absolute value is very small; as a direct consequence, the reference current will also be very small, and so their difference will be very small.
One way to avoid the incorrect reading of the cell state is to wait until the spurious capacitive current reaches zero value or almost a zero value. However, the time required to wait for this effect can be too much with regard to the desired reading performance of many systems.
Accordingly, a sense amplifier circuit that can reduce or cancel the dangerous effects of spurious capacitive current on reading the state of memory cells, even when such current is not yet negligible or zero, would be desirable in many applications.